A conventional buffered programmable interconnect point comprises an inverter feeding the source of an N-type field effect transistor, the gate of which is connected to a memory cell. The output of the memory cell determines whether the transistor is ON or OFF and thus whether or not the input to the inverter is passed through the transistor. The inverter comprises a complementary pair of CMOS transistors (i.e., N- and P-type having their respective gates connected to each other at the inverter input and also having their respective drains connected to each other at the inverter output). The P-transistor source is connected to a supply voltage and the N-transistor source is connected to ground. Normally, one or the other of the two transistors conducts depending on the voltage level of the input to the inverter. If the input voltage is high, corresponding to logic true, the N-transistor conducts, producing a logic low at the inverter output. If the input voltage is zero, corresponding to logic low, the P-transistor conducts, causing the output voltage to be raised to the supply voltage level, thereby producing a logic high at the inverter output.
However, a problem arises on both enabled and disabled programmable interconnect points while an input voltage is in transition. Specifically, during a voltage change at the input, both inverter transistors are momentarily in an ON state, thereby creating a current path from the supply voltage to ground (from the source of the P-transistor to the source of the N-transistor). This "crowbar current" problem is exacerbated when there are many buffered programmable interconnect point on one line such as on long signal paths or clock lines in an FPGA. If there is sufficient current flow through numerous such inverters the device consumes high power, and ground bounce can occur (i.e., ground is no longer truly zero volts). Ground bounce can cause inaccuracies and logic anomalies.
Accordingly, there is a need to provide buffered programmable interconnect points wherein a transition of the input signal does not enable a current path from the power line to the ground line.